1. Field of the Invention
The present invention relates to a dual mode accessing signal control apparatus for use in a memory and a dual mode timing signal generating apparatus. More particularly, the present invention relates to a dual mode accessing signal control apparatus capable of generating a shorter wordline width during a write process and a dual mode timing signal generating apparatus.
2. Descriptions of the Related Art
The most frequently used bitline tracking schemes of conventional static random access memories (SRAMs) are timing signal generating circuits. This bitline tracking scheme consists of a plurality of wordlines and a plurality of bitlines for use in a read process and a write process. The wordlines and bitlines intersect each other to form a plurality of memory cells. Generally, during the read process of the SRAM, the pulses on the wordlines must be of a sufficient width, so that a slight voltage swing is generated on the bitline signal and then a sense amplifier is used to correctly sense the data stored in the memory cells. In contrast, during the write process of the SRAM, the bitline voltage is decreased to the ground (GND) level. Finally, when the wordline pulse begins to fall, the bitline is precharged back to the VDD level. As a consequence, the whole cycle time of the read process and the write process are extended, which is especially the case when the memory capacity is relatively large.
FIGS. 1a and 1b depict a schematic view of a conventional SRAM scheme and the timing signal waveforms of a dummy column thereof respectively. For the circuit blocks that are not essentially related to the following description, the designations thereof are labeled in FIG. 1a directly for ease of understanding. At time t0, when a write actuating signal 113 is in an accessible state, a clock signal (CLK) 101 triggers a pulse start signal 102 to rise. The pulse start signal 102 reaches the highest level at time t1 to activate a dummy bitlines (DBLs) in the dummy column 11 so that a dummy bitline signal 103 begins to decrease while a wordline (WL) signal 105 begins to rise. At time t3, a dual-mode voltage detector 13 determines that the dummy bitline signal 103 is lower than a reference value, and then generates a pulse end signal 104. The pulse end signal 104 then pulls down the wordline signal 105 which previously stays at a high voltage level.
Furthermore, when being pulled down during the read process (i.e., between time t3 and t4), the wordline signal 105 has a width adapted to cause a slight voltage swing of about 200 mv on a bitline signal 107. A sense amplifier 13 then correctly senses data stored in the memory cells 15. Once the wordline signal 105 comes to an end at time t4, the precharging signal 106 begins to decrease while the bitline signal 107 of the read process starts precharging gradually, as depicted in FIG. 1b. 
However, during the write process, a bitline signal 108 of the write process stays at the GND level while the wordline signal 105 stays at a high voltage level. This continues until the wordline signal 105 comes to an end at time t4 when the bitline signal 108 begins to be precharged. As a result, it takes a long time for the bitline signal 108 to be restored to the high voltage level as depicted in FIG. 1b, which leads to a prolonged cycle time of the SRAM.
Accordingly, to solve the aforesaid problem, a solution in which different timing signals are provided in the read process and the write process respectively has been proposed in the prior art to shorten the cycle time. For example, U.S. Pat. No. 6,643,204 disclosed “a self-time scheme to reduce cycle time for memories”. According to this scheme, a cycle time delay of a wordline decoder, a cycle time delay of a dummy wordline relative to a dummy write cell, and a response time of the dummy write cell are utilized to detect the end of the write process to shorten the cycle time of the SRAM.
Another example is “a fast read/write cycle memory device having a self-timed read/write control circuit” as disclosed by U.S. Pat. No. 6,392,957. This patent is characterized by its read reference column and write reference column that are used to detect time points at which a read cycle and a write cycle end respectively. Two sense amplifiers are used to sense the end of the operations of the read reference columns according to a write-process-complete logic. In addition, a multiplexer is used to select outputs of the two sense amplifiers, while the sense amplifiers senses the operations of the read reference column according to the write process to determine a time point at which the read process ends. By controlling the dummy memory cells with a dummy wordline, the data rewrite operations of the write process are simulated and a complete signal is sent out to end the write process.
According to the disclosures of the aforesaid U.S. Pat. No. 6,643,204 and U.S. Pat. No. 6,392,957, although the read cycle time and the write cycle time can be shortened, the dummy write cell disclosed in U.S. Pat. No. 6,643,204 and the dummy memory cell disclosed in U.S. Pat. No. 6,392,957 can only reflect an average value of the write cycle time of the memory cells but fail to reflect the longest write cycle time. Consequently, it is impossible for the memory cells to sense the data stored therein in a quite correct way. Moreover, the invention disclosed in U.S. Pat. No. 6,392,957 requires too large of a chip area, which is impractical in application.
In view of this, it is important to read or write data in a quick and correct way to shorten the cycle time of a memory and reduce the area of a chip while still ensuring good performance thereof.